Static random access memories (SRAM) are commonly used in integrated circuits. Embedded SRAM is popular in high speed communication, image processing and system-on-chip (SOC) applications. SRAM cells have the advantageous feature of holding data without requiring a refresh. Typically, a SRAM cell includes two pass-gate transistors, through which a bit can be read from or written into the SRAM cell. This type of SRAM cell is referred to as a single port SRAM cell. Another type of SRAM cell is referred to as a dual port SRAM cell, which includes four pass-gate transistors. With two ports, the bit stored in the SRAM cell can be read from port-A and port-B simultaneously. This allows for parallel operations by different applications. Moreover, if a first SRAM cell and a second SRAM cell are in a same column or a same row, a read operation from the first SRAM cell can also be performed simultaneously with a write operation to the second SRAM cell.
As timing and voltage margins have reduced, operational errors can occur. One type of error is called “read-disturb-write”. Assume for example a first SRAM cell in a row is being written to on Port A. If the Port B word line is active, for example so that a read or write operation can occur to the Port B of a second cell, then the Port B of the first cell is under a “dummy read” condition. This dummy read condition may induce error in the write operation to the Port A of the first SRAM cell.